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Datasheet File OCR Text:

M95160-x M95080-x
16 Kbit and 8 Kbit serial SPI bus EEPROM with high speed clock
Features

Compatible with SPI bus serial interface (positive clock SPI modes) Single supply voltage: - 4.5 V to 5.5 V for M95xxx - 2.5 V to 5.5 V for M95xxx-W - 1.8 V to 5.5 V for M95xxx-R - 1.7 V to 5.5 V for M95xxx-F High speed: 10 MHz Status Register Hardware protection of the Status Register Byte and page write (up to 32 bytes) Self-timed programming cycle Adjustable size read-only EEPROM area Enhanced ESD protection More than 1 million write cycles More than 40-year data retention Packages - ECOPACK(R) (RoHS compliant) Device summary
Part number M95160 M95160-W M95160-x M95160-R M95160-F M95080 M95080-x M95080-W M95080-R
1. Preliminary data.
SO8 (MN) 150 mil width

TSSOP8 (DW) 169 mil width
UFDFPN8 (MB) 2 x 3 mm (MLP)
Table 1.
Reference
WLCSP (CS)1)
October 2009
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www.st.com 1
Contents
M95160-x, M95080-x
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 4.1.2 4.1.3 4.1.4 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2 4.3 4.4 4.5
Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 6.2 6.3 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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Contents WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 6.5 6.6
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7
Delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.1 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8 9 10 11 12
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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List of tables
M95160-x, M95080-x
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Operating conditions (M95160 and M95080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95160-W and M95080-W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating conditions (M95160-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 27 DC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 28 DC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 29 DC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC characteristics (M95160-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AC characteristics (M95160 and M95080, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . 32 AC characteristics (M95160 and M95080, device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . 33 AC characteristics (M95160-W and M95080-W, device grade 3). . . . . . . . . . . . . . . . . . . . 34 AC characteristics (M95160-W and M95080-W, device grade 6). . . . . . . . . . . . . . . . . . . . 35 AC characteristics for M95160-Wxx6/S and M95080-Wxx6/S . . . . . . . . . . . . . . . . . . . . . . 36 AC characteristics (M95160-R and M95080-R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 AC characteristics (M95160-F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SO8N - 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 41 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 WLCSP-R 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 TSSOP8 - 8-lead thin shrink small outline, package mechanical data. . . . . . . . . . . . . . . . 44 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Available M95160 products (package, voltage range, temperature grade) . . . . . . . . . . . . 46 Available M95080 products (package, voltage range, temperature grade) . . . . . . . . . . . . 46 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 M95160 WLCSP connections (top view, marking side, with balls on the underside) . . . . . . 7 Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SO8N - 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 41 UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 WLCSP-R 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package outline . . . . . . . . . . . . . . . 43 TSSOP8 - 8-lead thin shrink small outline, package outline . . . . . . . . . . . . . . . . . . . . . . . 44
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Description
M95160-x, M95080-x
1
Description
The M95160-x and M95080-x are electrically erasable programmable memory (EEPROM) devices. They are accessed by a high-speed SPI-compatible bus. The memory array is organized as 2048 x 8 bit (M95160-x), and 1024 x 8 bit (M95080-x). The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2 and Figure 1. The device is selected when Chip Select (S) is taken low. Communications with the device can be interrupted using Hold (HOLD). Figure 1. Logic diagram
VCC
D C S W HOLD M95xxx
Q
VSS
AI01789C
Table 2.
Signal names
Function Serial Clock Serial Data input Serial Data output Chip Select Write Protect Hold Supply voltage Ground Input Input Output Input Input Input Direction
Signal name C D Q S W HOLD VCC VSS
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M95xxx S Q W VSS 1 2 3 4 8 7 6 5
AI01790D
Description
VCC HOLD C D
1. See Package mechanical data section for package dimensions, and how to identify pin-1.
Figure 3.
M95160 WLCSP connections (top view, marking side, with balls on the underside)
Q
VSS
W
S
D
HOLD
VCC
C
Orientation reference
ai15166
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Signal description
M95160-x, M95080-x
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Signal description
During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 14. to Table 19.). These signals are described next.
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C).
2.2
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be written. Values are latched on the rising edge of Serial Clock (C).
2.3
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
2.4
Chip Select (S)
When this input signal is high, the device is deselected and Serial Data Output (Q) is at high impedance. Unless an internal Write cycle is in progress, the device will be in the Standby Power mode. Driving Chip Select (S) low selects the device, placing it in the Active Power mode. After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
2.5
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven low.
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Signal description
2.6
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all write instructions.
2.7
VCC supply voltage
VCC is the supply voltage.
2.8
VSS ground
VSS is the reference for the VCC supply voltage.
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Connecting to the SPI bus
M95160-x, M95080-x
3
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first. The Serial Data output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 4. shows three devices, connected to an MCU, on an SPI bus. Only one device is selected at a time, so only one device drives the Serial Data output (Q) line at a time, all the others being high impedance. Figure 4. Bus master and memory devices on the SPI bus
VSS VCC R SDO SPI Interface with (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK CQD SPI Bus Master R CS3 CS2 CS1 S W HOLD S W HOLD S W HOLD SPI Memory Device VCC VSS R SPI Memory Device CQD VCC VSS R SPI Memory Device CQD VCC VSS
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an MCU, on an SPI bus. Only one memory device is selected at a time, so only one memory device drives the Serial Data output (Q) line at a time, the other memory devices are high impedance. The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the Bus Master leaves the S line in the high impedance state. In applications where the Bus Master may be in a state where all input/output SPI buses are high impedance at the same time (for example, if the Bus Master is reset during the transmission of an instruction), the clock line (C) must be connected to an external pulldown resistor so that, if all inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled high): this ensures that S and C do not become high at the same time, and so, that the tSHCH requirement is met. The typical value of R is 100 k.
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Connecting to the SPI bus
3.1
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:

CPOL=0, CPHA=0 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5., is the clock polarity when the bus master is in Stand-by mode and not transferring data:

C remains at 0 for (CPOL=0, CPHA=0) C remains at 1 for (CPOL=1, CPHA=1) SPI modes supported
Figure 5.
CPOL CPHA
0
0
C
1
1
C
D
MSB
Q
MSB
AI01438B
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Operating features
M95160-x, M95080-x
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4.1
4.1.1
Operating features
Supply voltage (VCC)
Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Table 9, Table 10 and Table 11). This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
4.1.2
Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC reaches the POR threshold voltage (this threshold is defined in DC characteristics tables 15, 16, 17, 18, 19 and 20 as VRES). When VCC passes over the POR threshold, the device is reset and is in the following state:

in Standby Power mode deselected (note that, to be executed, an instruction must be preceded by a falling edge on Chip Select (S)) Status Register value: - - - the Write Enable Latch (WEL) is reset to 0 Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits)
When VCC passes over the POR threshold, the device is reset and enters the Standby Power mode. The device must not be accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range defined in Table 9, Table 10 and Table 11.
4.1.3
Power-up conditions
When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 4). In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select (S) must have been high, prior to going low to start the first operation. The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage defined in Table 9, Table 10 and Table 11 and the rise time must not vary faster than 1 V/s.
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Operating features
4.1.4
Power-down
During power-down (continuous decrease in the VCC supply voltage below the minimum VCC operating voltage defined in Table 9, Table 10 and Table 11), the device must be:

deselected (Chip Select S should be allowed to follow the voltage applied on VCC) in Standby Power mode (there should not be any internal write cycle in progress).
4.2
Active Power and Standby Power modes
When Chip Select (S) is low, the device is selected, and in the Active Power mode. The device consumes ICC, as specified in Table 14. to Table 19. When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in progress, the device then goes into the Standby Power mode, and the device consumption drops to ICC1.
4.3
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don't Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low. Normally, the device is kept selected, for the whole duration of the Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as Serial Clock (C) already being low. The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as Serial Clock (C) already being low.
4.4
Status Register
Figure 6. shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a detailed description of the Status Register bits
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Operating features
M95160-x, M95080-x
4.5
Data protection and protocol control
Non-volatile memory devices can be used in environments that are particularly noisy, and within applications that could experience problems if memory bytes are corrupted. Consequently, the device features the following data protection mechanisms:

Write and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state by the following events: - - - - Power-up Write Disable (WRDI) instruction completion Write Status Register (WRSR) instruction completion Write (WRITE) instruction completion

The Block Protect (BP1, BP0) bits in the Status Register allow part of the memory to be configured as read-only. The Write Protect (W) signal allows the Block Protect (BP1, BP0) bits of the Status Register to be protected.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising edge of Serial Clock (C). Two points need to be noted in the previous sentence:
The `last bit of the instruction' can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). The `next rising edge of Serial Clock (C)' might (or might not) be the next bus transaction for some other device on the SPI bus. Write-protected block size
Protected array addresses Protected block BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory M95160-x none 0600h - 07FFh 0400h - 07FFh 0000h - 07FFh M95080-x none 0300h - 03FFh 0200h - 03FFh 0000h - 03FFh
Table 3.
Status Register bits
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Memory organization
5
Memory organization
The memory is organized as shown in Figure 6. Figure 6. Block diagram
HOLD W S C D Q Control logic
High voltage generator
I/O shift register
Address register and counter
Data register Status Register
Size of the read-only EEPROM area
Y decoder
1 page
X decoder
AI01272d
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Instructions
M95160-x, M95080-x
6
Instructions
Each instruction starts with a single-byte code, as summarized in Table 4. If an invalid instruction is sent (one not contained in Table 4.), the device automatically deselects itself. Table 4. Instruction set
Description Write Enable Write Disable Read Status Register Write Status Register Read from Memory Array Write to Memory Array Instruction format 0000 0110 0000 0100 0000 0101 0000 0001 0000 0011 0000 0010
Instruction WREN WRDI RDSR WRSR READ WRITE
6.1
Write Enable (WREN)
The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7., to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven high. Figure 7. Write Enable (WREN) sequence
S 0 C Instruction D High Impedance Q
AI02281E
1
2
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7
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Instructions
6.2
Write Disable (WRDI)
One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 8., to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high. The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:

Power-up WRDI instruction execution WRSR instruction completion WRITE instruction completion. Write Disable (WRDI) sequence
S 0 C Instruction D High Impedance Q
AI03750D
Figure 8.
1
2
3
4
5
6
7
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Instructions
M95160-x, M95080-x
6.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. The status and control bits of the Status Register are as follows:
6.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
6.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write or Write Status Register instruction is accepted.
6.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 5.) becomes protected against Write (WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
6.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution. Table 5.
b7 SRWD 0 0 0 BP1 BP0 WEL
Status Register format
b0 WIP
Status Register Write Protect Block Protect Bits Write Enable Latch Bit Write In Progress Bit
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M95160-x, M95080-x Figure 9.
S 0 C Instruction D Status Register Out High Impedance Q 7 MSB 6 5 4 3 2 1 0 7 MSB 6 5 4 3 2 1 Status Register Out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instructions Read Status Register (RDSR) sequence
0
7
AI02031E
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Instructions
M95160-x, M95080-x
6.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S) driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise, the Write Status Register (WRSR) instruction is not executed. The instruction sequence is shown in Figure 10. Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed write cycle that takes tW to complete (as specified in Table 21, Table 22, Table 23, Table 24, Table 26 and Table 27). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write cycle tW, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also reset at the end of the write cycle tW. The Write Status Register (WRSR) instruction allows the user to change the values of the BP1, BP0 and SRWD bits:

The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as read only, as defined in Table 3. The SRWD bit (Status Register Write Disable bit), in accordance with the signal read on the Write Protect pin (W), allows the user to set or reset the Write protection mode of the Status Register itself, as defined in Table 6. When in Write-protected mode, the Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction, including the tW Write cycle. The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the Status Register. Bits b6, b5, b4 are always read as 0. Table 6. Protection modes
Mode Write protection of the Status Register Memory content Protected area(1) Unprotected area(1)
W SRWD signal bit 1 0 0 0
1
1
Status Register is writable (if the WREN Software- instruction has set the protected WEL bit) (SPM) The values in the BP1 and BP0 bits can be changed
Write-protected
Ready to accept Write instructions
0
1
Status Register is Hardware- Hardware write-protected protected The values in the BP1 Write-protected (HPM) and BP0 bits cannot be changed
Ready to accept Write instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.
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M95160-x, M95080-x The protection features of the device are summarized in Table 6.
Instructions
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction), regardless of the logic level applied on the Write Protect (W) input pin. When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two cases need to be considered, depending on the state of the Write Protect (W) input pin:

If Write Protect (W) is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction. If Write Protect (W) is driven low, it is not possible to write to the Status Register even if the WEL bit has previously been set by a WREN instruction. (Attempts to write to the Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area, which are software-protected (SPM) by the Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered by:

either setting the SRWD bit after driving the Write Protect (W) input pin low or driving the Write Protect (W) input pin low after setting the SRWD bit
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the Write Protect (W) input pin. If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode (HPM) can never be activated, and only the Software-protected mode (SPM), using the Block Protect (BP1, BP0) bits in the Status Register, can be used. Table 7. Address range bits(1)
Device Address bits
1. b15 to b11 are Don't Care on the M95160-x. b15 to b10 are Don't Care on the M95080-x.
M95160-x A10-A0
M95080-x A9-A0
Figure 10. Write Status Register (WRSR) sequence
S 0 C Instruction Status Register In 7 High Impedance Q
AI02282D
1
2
3
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5
6
7
8
9 10 11 12 13 14 15
D
6
5
4
3
2
1
0
MSB
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Instructions
M95160-x, M95080-x
6.5
Read from Memory Array (READ)
As shown in Figure 11., to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). If Chip Select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of data at the new address is shifted out. When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
Figure 11. Read from Memory Array (READ) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13 MSB
3
2
1
0 Data Out 1 7 6 5 4 3 2 1 0 Data Out 2 7
MSB
AI01793D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don't Care.
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Instructions
6.6
Write to Memory Array (WRITE)
As shown in Figure 12., to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a period tW (as specified in Table 22. to Table 26.), at the end of which the Write in Progress (WIP) bit is reset to 0. In the case of Figure 12., Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. If, though, Chip Select (S) continues to be driven low, as shown in Figure 13., the next byte of input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal Write cycle. Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 32 bytes). The instruction is not accepted, and is not executed, under the following conditions:

if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before) if a Write cycle is already in progress if the device has not been deselected, by Chip Select (S) being driven high, at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in) if the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Note:
The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as "0" and a programmed bit is read as "1". Figure 12. Byte Write (WRITE) sequence
S 0 C Instruction 16-Bit Address Data Byte 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
D High Impedance Q
15 14 13
3
2
1
0
7
6
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0
AI01795D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don't Care.
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Instructions Figure 13. Page Write (WRITE) sequence
S 0 C Instruction 16-Bit Address 1 2 3 4 5 6 7 8 9 10
M95160-x, M95080-x
20 21 22 23 24 25 26 27 28 29 30 31
Data Byte 1
D
15 14 13
3
2
1
0
7
6
5
4
3
2
1
0
S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 Data Byte 3 Data Byte N
D
7
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AI01796D
1. Depending on the memory size, as shown in Table 7., the most significant address bits are Don't Care.
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Delivery state
7
7.1
Delivery state
Initial delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
8
Maximum rating
Stressing the device outside the ratings listed in Table 8. may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8.
Symbol TA TSTG TLEAD VO VI VCC VESD
Absolute maximum ratings
Parameter Ambient operating temperature Storage temperature Lead temperature during soldering Output voltage Input voltage Supply voltage Electrostatic discharge voltage (human body model)(2) Min. -40 -65 Max. 130 150 Unit C C C V V V V
(R)
See note (1) -0.50 -0.50 -0.50 -4000 VCC+0.6 6.5 6.5 4000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU 2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 , R2=500 )
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DC and AC parameters
M95160-x, M95080-x
9
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 9.
Symbol VCC TA Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 3)
Operating conditions (M95160 and M95080)
Parameter Min. 4.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 10.
Symbol VCC TA
Operating conditions (M95160-W and M95080-W)
Parameter Supply voltage Ambient operating temperature (device grade 6) Ambient operating temperature (device grade 3) Min. 2.5 -40 -40 Max. 5.5 85 125 Unit V C C
Table 11.
Symbol VCC TA
Operating conditions (M95160-R and M95080-R)
Parameter Supply voltage Ambient operating temperature Min. 1.8 -40 Max. 5.5 85 Unit V C
Table 12.
Symbol VCC TA
Operating conditions (M95160-F)(1)
Parameter Supply voltage Ambient operating temperature Min. 1.7 -40 Max. 5.5 85 Unit V C
1. Preliminary data.
Table 13.
Symbol CL
AC measurement conditions(1)
Parameter Load capacitance Input rise and fall times Input pulse voltages Input and output timing reference voltages Min. Typ. 30 50 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC Max. Unit pF ns V V
1. Output Hi-Z is defined as the point where data out is no longer driven.
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M95160-x, M95080-x Figure 14. AC measurement I/O waveform
Input Levels 0.8VCC
DC and AC parameters
Input and Output Timing Reference Levels 0.7VCC 0.3VCC
AI00825B
0.2VCC
Table 14.
Symbol COUT CIN
Capacitance(1)
Parameter Output capacitance (Q) Input capacitance (D) Input capacitance (other pins) Test condition VOUT = 0 V VIN = 0 V VIN = 0 V Min. Max. 8 8 6 Unit pF pF pF
1. Sampled only, not 100% tested, at TA = 25 C and a frequency of 5 MHz.
Table 15.
Symbol ILI ILO ICC ICC1 VIL VIH VOL
(1)
DC characteristics (M95160 and M95080, device grade 3)
Parameter Input leakage current Output leakage current Supply current Test condition VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 5 V, Q = open Min. Max. 2 2 3 5 -0.45 0.7 VCC IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC 2.5 3.5 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V V
Supply current (Standby) S = VCC, VCC = 5 V, VIN = VSS or VCC Input low voltage Input high voltage Output low voltage
VOH (1) Output high voltage VRES(2) Internal reset threshold voltage
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards. 2. Characterized only, not 100% tested.
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DC and AC parameters Table 16.
Symbol ILI ILO ICC ICC1 VIL VIH VOL(1) VOH
(1)
M95160-x, M95080-x DC characteristics (M95160 and M95080, device grade 6)
Parameter Test conditions VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 10 MHz, VCC = 5 V, Q = open S = VCC, VCC = 5 V, VIN = VSS or VCC -0.45 0.7 VCC IOL = 2 mA, VCC = 5 V IOH = -2 mA, VCC = 5 V 0.8 VCC 2.5 3.5 Min. Max. 2 2 5 2 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V V
Input leakage current Output leakage current Supply current Supply current (Standby) Input low voltage Input high voltage Output low voltage Output high voltage Internal reset threshold voltage
VRES(2)
1. For all 5 V range devices, the device meets the output requirements for both TTL and CMOS standards. 2. Characterized only, not 100% tested.
Table 17.
Symbol ILI ILO ICC ICC1 VIL VIH VOL VOH VRES(1)
DC characteristics (M95160-W and M95080-W, device grade 3)
Parameter Input leakage current Output leakage current Supply current Supply current (Standby) Input low voltage Input high voltage Output low voltage IOL = 1.5 mA, VCC = 2.5 V 0.8 VCC 1.0 1.65 Test conditions VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5 V, Q = open S = VCC, VCC = 2.5 V, VIN = VSS or VCC -0.45 0.7 VCC Min. Max. 2 2 2 2 0.3 VCC VCC+1 0.4 Unit A A mA A V V V V V
Output high voltage IOH = -0.4 mA, VCC = 2.5 V Internal reset threshold voltage
1. Characterized only, not 100% tested.
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M95160-x, M95080-x Table 18.
Symbol ILI ILO
DC and AC parameters DC characteristics (M95160-W and M95080-W, device grade 6)
Parameter Input leakage current Output leakage current Test conditions VIN = VSS or VCC S = VCC, VOUT = VSS or VCC C = 0.1VCC/0.9VCC at 5 MHz, VCC = 2.5V, Q = open, Process SA Min. Max. 2 2 2 Unit A A mA
ICC
Supply current
C = 0.1VCC/0.9VCC at 10 MHz, VCC = 2.5 V, Q = open, Process GB or SB S = VCC, 2.5 V 5
mA
ICC1 VIL VIH VOL VOH VRES(1)
Supply current (Standby) Input low voltage Input high voltage Output low voltage
2 0.3 VCC VCC+1 0.4
A V V V V
Output high voltage IOH = -0.4 mA, VCC = 2.5 V Internal reset threshold voltage
1.65
V
1. Characterized only, not 100% tested.
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DC and AC parameters Table 19.
Symbol ILI ILO
M95160-x, M95080-x DC characteristics (M95160-R and M95080-R)(1)
Parameter Test conditions VIN = VSS or VCC S = VCC, voltage applied on Q = VSS or VCC VCC = 2.5 V, C = 0.1 VCC or 0.9VCC, fC = 5 MHz, Q = open VCC = 1.8 V, C = 0.1VCC or 0.9VCC at max clock frequency, Q = open VCC = 5.0 V, S = VCC, VIN = VSS or VCC Min. Max. 2 2 3 2 2 1 1 -0.45 -0.45 0.7VCC 0.75VCC 0.3VCC 0.25VCC VCC+1 VCC+1 0.2VCC 0.3 0.8VCC Unit A A mA mA A A A V V V V V V V
Input leakage current Output leakage current
ICCR
Supply current (Read)
ICC1
Supply current (Standby)
VCC = 2.5 V, S = VCC, VIN = VSS or VCC VCC = 1.8 V, S = VCC, VIN = VSS or VCC
VIL
Input low voltage
2.5V < VCC < 5.5V 1.8V < VCC < 2.5V
VIH
Input high voltage
2.5V < VCC < 5.5V 1.8V < VCC < 2.5V
VOL
Output low voltage
VCC = 2.5 V, IOL = 1.5 mA, or VCC = 5.5 V, IOL = 2 mA VCC = 1.8 V, IOL = 0.15 mA
VOH
VCC = 2.5 V, IOH = -0.4 mA, Output high voltage or VCC = 5.5 V, IOH = -2 mA, or VCC = 1.8 V, IOH = -0.1 mA Internal reset threshold voltage
VRES(2)
1.0
1.65
V
1. If the application uses the M95080-R and M95160-R at 2.5 V VCC 5.5 V and -40 C TA +85 C, please refer to Table 16: DC characteristics (M95160 and M95080, device grade 6) instead of the above table. 2. Characterized only, not 100% tested.
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M95160-x, M95080-x Table 20.
Symbol ILI ILO
DC and AC parameters DC characteristics (M95160-F)
Parameter Test conditions Min. Max. 2 2 3 2 2 1 1 -0.45 -0.45 -0.45 0.7VCC 0.75VCC 0.3VCC 0.25VCC 0.20VCC VCC+1 VCC+1 0.2VCC 0.2 0.8VCC Unit A A mA mA A A A V V V V V V V V
Input leakage current VIN = VSS or VCC Output leakage current S = VCC, voltage applied on Q = VSS or VCC VCC = 2.5 V, C = 0.1 VCC or 0.9VCC, fC = 5 MHz, Q = open VCC = 1.7 V, C = 0.1VCC or 0.9VCC at max clock frequency, Q = open VCC = 5.0 V, S = VCC, VIN = VSS or VCC
ICCR
Supply current (Read)
ICC1
Supply current (Standby)
VCC = 2.5 V, S = VCC, VIN = VSS or VCC VCC = 1.7 V, S = VCC, VIN = VSS or VCC 2.5 V < VCC < 5.5 V
VIL
Input low voltage
1.8 < VCC < 2.5 V 1.7 V < VCC < 1.8 V
VIH
Input high voltage
2.5 V < VCC < 5.5 V 1.7 V < VCC < 2.5 V
VOL
Output low voltage
VCC = 2.5 V, IOL = 1.5 mA, or VCC = 5.5 V, IOL = 2 mA VCC = 1.7 V, IOL = 0.15 mA
VOH
Output high voltage Internal reset threshold voltage
VCC = 2.5 V, IOH = -0.4 mA, or VCC = 5.5 V, IOH = -2 mA, or VCC = 1.7 V, IOH = -0.1 mA
VRES(1)
1.0
1.65
V
1. Characterized only, not 100% tested.
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DC and AC parameters Table 21.
M95160-x, M95080-x AC characteristics (M95160 and M95080, device grade 3)
Test conditions specified in Table 13. and Table 9.
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL
(1)) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active
tCLCH tCHCL
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ(2) tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production.
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M95160-x, M95080-x Table 22.
DC and AC parameters AC characteristics (M95160 and M95080, device grade 6)
Test conditions specified in Table 13. and Table 9.
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL
(1) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Min. D.C. 15 15 40 25 15 40 40
Max. 10
Unit MHz ns ns ns ns ns ns ns
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active
tCLCH tCHCL
1 1 15 15 15 20 0 0 25 35 0 20 20 25 35 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write Time
tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ ((2)) tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Table 23.
M95160-x, M95080-x AC characteristics (M95160-W and M95080-W, device grade 3)
Test conditions specified in Table 13. and Table 10.
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL(1) tCLCH tCHCL
(2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency S active setup time
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ(2) tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ(2) tW
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production.
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M95160-x, M95080-x Table 24.
DC and AC parameters AC characteristics (M95160-W and M95080-W, device grade 6)
Test conditions specified in Table 13. and Table 10.
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL
(1) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH
Parameter Clock frequency S active setup time S not active setup time S deselect time S active hold time S not active hold time
Min. D.C. 30 30 40 30 30 40 40
Max. 10
Unit MHz ns ns ns ns ns ns ns
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active
tCLCH tCHCL
2 2 10 10 30 30 0 0 40 40(3) 0 40 40 40 40 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ(2) tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ(2) tW
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production. 3. tCLQV must be compatible with tCL (clock low time): if the SPI bus master offers a Read setup time tSU = 0 ns, tCL can be equal to (or greater than) tCLQV. In all other cases, tCL must be equal to (or greater than) tCLQV + tSU.
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DC and AC parameters Table 25.
M95160-x, M95080-x AC characteristics for M95160-Wxx6/S and M95080-Wxx6/S
Test conditions specified in Table 10 and Table 13
Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL
(1) (2) (2)
Alt. fSCK tCSS1 tCSS2 tCS tCSH Clock frequency
Parameter
Min. D.C. 90 90 100 90 90 90 90
Max. 5
Unit MHz ns ns ns ns ns ns ns
S active setup time S not active setup time S deselect time S active hold time S not active hold time
tCLH tCLL tRC tFC tDSU tDH
Clock high time Clock low time Clock rise time Clock fall time Data in setup time Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active
tCLCH tCHCL
1 1 20 30 70 40 0 0 100 60 0 50 50 50 100 5
s s ns ns ns ns ns ns ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ(2) tCLQV tCLQX tQLQH tQHQL
(2) (2)
tDIS tV tHO tRO tFO tLZ tHZ tWC
Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tHHQV tHLQZ(2) tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production.
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M95160-x, M95080-x Table 26. AC characteristics (M95160-R and M95080-R)
DC and AC parameters
Test conditions specified in Table 13 and Table 11 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(1) tCL
(1) (2) (2)
Alt. fSCK Clock frequency tCSS1 S active setup time
Parameter
Min. D.C. 60 60 90 60 60 80 80
Max. 5
Unit MHz ns ns ns ns ns ns ns
tCSS2 S not active setup time tCS S deselect time
tCSH S active hold time S not active hold time tCLH Clock high time tCLL Clock low time tRC tFC Clock rise time Clock fall time
tCLCH tCHCL
2 2 20 20 60 60 0 0 80 80 0 80 80 80 80 5
s s ns ns ns ns 0 0 ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDSU Data in setup time tDH Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active tDIS tV tHO tRO tFO tLZ tHZ tWC Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ(2) tW
1. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 2. Value guaranteed by characterization, not 100% tested in production.
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DC and AC parameters Table 27. AC characteristics (M95160-F)(1)
Test conditions specified in Table 12 Symbol fC tSLCH tSHCH tSHSL tCHSH tCHSL tCH(2) tCL
(1) (3) (2)
M95160-x, M95080-x
Alt. fSCK Clock frequency tCSS1 S active setup time
Parameter
Min. D.C. 85 85 120 85 85 110 110
Max. 3.5
Unit MHz ns ns ns ns ns ns ns
tCSS2 S not active setup time tCS S deselect time
tCSH S active hold time S not active hold time tCLH Clock high time tCLL Clock low time tRC tFC Clock rise time Clock fall time
tCLCH tCHCL
2 2 30 30 85 85 0 0 120 120 0 100 100 110 110 5
s s ns ns ns ns 0 0 ns ns ns ns ns ns ns ms
tDVCH tCHDX tHHCH tHLCH tCLHL tCLHH tSHQZ
(2)
tDSU Data in setup time tDH Data in hold time Clock low hold time after HOLD not active Clock low hold time after HOLD active Clock low set-up time before HOLD active Clock low set-up time before HOLD not active tDIS tV tHO tRO tFO tLZ tHZ tWC Output disable time Clock low to output valid Output hold time Output rise time Output fall time HOLD high to output valid HOLD low to output high-Z Write time
tCLQV tCLQX tQLQH(2) tQHQL(2) tHHQV tHLQZ(2) tW
1. Preliminary data. 2. tCH + tCL must never be lower than the shortest possible clock period, 1/fC(max). 3. Value guaranteed by characterization, not 100% tested in production.
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M95160-x, M95080-x Figure 15. Serial input timing
DC and AC parameters
tSHSL S tCHSL C tDVCH tCHCL tCHDX D MSB IN LSB IN tCL tCLCH tSLCH tCH tCHSH tSHCH
Q
High impedance
AI01447d
Figure 16. Hold timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQV tHHCH
HOLD
AI01448c
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DC and AC parameters Figure 17. Serial output timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D LSB IN
ADDR
M95160-x, M95080-x
tSHSL
tCLCH
tCHCL
tCL
tSHQZ
AI01449f
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M95160-x, M95080-x
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Figure 18. SO8N - 8-lead plastic small outline, 150 mils body width, package outline
h x 45 A2 b e 0.25 mm GAUGE PLANE k
8
A ccc c
D
E1
1
E A1 L L1
SO-A
1. Drawing is not to scale.
Table 28.
Symbol
SO8N - 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters Typ Min Max 1.75 0.1 1.25 0.28 0.17 0.48 0.23 0.1 4.9 6 3.9 1.27 4.8 5.8 3.8 0.25 0 0.4 1.04 5 6.2 4 0.5 8 1.27 0.0409 0.1929 0.2362 0.1535 0.05 0.189 0.2283 0.1496 0.0098 0 0.0157 0.25 0.0039 0.0492 0.011 0.0067 0.0189 0.0091 0.0039 0.1969 0.2441 0.1575 0.0197 8 0.05 Typ inches(1) Min Max 0.0689 0.0098
A A1 A2 b c ccc D E E1 e h k L L1
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Package mechanical data
M95160-x, M95080-x
Figure 19. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, package outline
D L3 e b L1
E
E2
L A D2 ddd A1
UFDFPN-01
1. Drawing is not to scale. 2. The central pad (the area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process.
Table 29.
UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 x 3 mm, package mechanical data
millimeters inches(1) Max 0.6 0.05 0.3 2.1 1.7 3.1 0.3 0.5 0.15 0.3 0.08 0.0118 0.08 Typ 0.0217 0.0008 0.0098 0.0787 0.063 0.1181 0.0079 0.0197 0.0177 Min 0.0177 0 0.0079 0.0748 0.0591 0.1142 0.0039 0.0157 Max 0.0236 0.002 0.0118 0.0827 0.0669 0.122 0.0118 0.0197 0.0059
Symbol Typ A A1 b D D2 E E2 e L L1 L3 ddd
(2)
Min 0.45 0 0.2 1.9 1.5 2.9 0.1 0.4
0.55 0.02 0.25 2 1.6 3 0.2 0.5 0.45
1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.
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Package mechanical data
Figure 20. WLCSP-R 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package outline
e1 D e G
C
Detail A
e B e1
E
Orientation reference
A Orientation reference aaa Wafer back side (x4) A2 Bump A1 Side view A F
3
2 Bump side
1
eee Z
b Detail A Rotated 90
Z Seating plane (see note 1)
1C_ME
1. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 2. Drawing is not to scale. 3. Preliminary data.
Table 30.
WLCSP-R 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical data(1)
millimeters inches(2) Max 0.600 Typ 0.0193 0.0075 0.014 0.240 0.300 1.475 1.490 0.0106 0.0531 0.0537 0.0157 0.0315 0.0111 0.0108 8 0.110 0.060 8 0.0043 0.0024 0.0094 0.0118 0.0581 0.0587 Min 0.0215 Max 0.0236
Symbol Typ A A1 A2 b
(3)
Min 0.490
0.545 0.190 0.355 0.270 1.350 1.365 0.400 0.800 0.282 0.275
D E e e1 F G N (total number of terminals) aaa eee
1. Preliminary data.
2. Values in inches are converted from mm and rounded to 4 decimal digits. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
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Package mechanical data
M95160-x, M95080-x
Figure 21. TSSOP8 - 8-lead thin shrink small outline, package outline
D
8
5
c
E1 E
1
4
A1 A CP b e A2
L L1
TSSOP8AM
1. Drawing is not to scale.
Table 31.
Symbol
TSSOP8 - 8-lead thin shrink small outline, package mechanical data
millimeters Typ Min Max 1.2 0.05 1 0.8 0.19 0.09 0.15 1.05 0.3 0.2 0.1 3 0.65 6.4 4.4 0.6 1 0 8 8 2.9 6.2 4.3 0.45 3.1 6.6 4.5 0.75 0.1181 0.0256 0.252 0.1732 0.0236 0.0394 0 8 8 0.1142 0.2441 0.1693 0.0177 0.0394 0.002 0.0315 0.0075 0.0035 Typ inches(1) Min Max 0.0472 0.0059 0.0413 0.0118 0.0079 0.0039 0.122 0.2598 0.1772 0.0295
A A1 A2 b c CP D e E E1 L L1 N
1. Values in inches are converted from mm and rounded to 4 decimal digits.
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Part numbering
11
Part numbering
Table 32.
Example: Device type M95 = SPI serial access EEPROM Device function 160 = 16 Kbit (2048 x 8) 080 = 8 Kbit (1024 x 8) Operating voltage blank = VCC = 4.5 to 5.5 V W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.5 V Package MN = SO8 (150 mil width) DW = TSSOP8 MB = MLP8 (UFDFPN8) CS = WLCSP(1) Device grade 6 = Industrial temperature range, -40 to 85 C. Device tested with standard test flow 3 = Device tested with high reliability certified flow(2). Automotive temperature range (-40 to 125 C) Option blank = Standard packing T = Tape and reel packing Plating technology G or P = ECOPACK(R) (RoHS compliant) Process(3) /G or /S = F6SP36%
1. Preliminary data. 2. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The high reliability certified flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy. 3. The Process letter (/G or /S) applies only to Range 3 devices. For Range 6 devices, the process letters do not appear in the Ordering Information but only appear on the device package (marking) and on the shipment box. Please contact your nearest ST Sales Office. For more information on how to identify products by the Process Identification Letter, please refer to AN2043: Serial EEPROM Device Marking.
Ordering information scheme
M95160 - W MN 6 T P /S
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Part numbering
M95160-x, M95080-x
For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 33. Available M95160 products (package, voltage range, temperature grade)
M95160 4.5 V to 5.5 V Range 6 Range3 NA(1) NA(1) NA(1) M95160-W 2.5 V to 5.5 V Range 6 Range3 Range 6 Range3 NA(1) NA(1) M95160-R 1.8 V to 5.5 V Range 6 Range 6 Range 6 Range 6 M95160-F 1.7 V to 5.5 V NA(1) Range 6 NA(1) Range 6
Package
SO8 (MN) TSSOP (DW) MLP 2 x 3 mm (MB) WLCSP (CS)
1. NA = Not available
Table 34.
Available M95080 products (package, voltage range, temperature grade)
M95080 4.5 V to 5.5 V Range 6 Range3 NA(1) NA(1) M95080-W 2.5 V to 5.5 V Range 6 Range3 Range 6 Range3 Range 6 M95080-R 1.8 V to 5.5 V Range 6 Range 6 Range 6
Package
SO8 (MN) TSSOP (DW) MLP 2 x 3mm (MB)
1. NA = Not available
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Revision history
12
Revision history
Table 35.
Date 19-Jul-2001 06-Feb-2002 18-Oct-2002 04-Nov-2002 13-Nov-2002 21-Nov-2003
Document revision history
Revision 1.0 1.1 1.2 1.3 1.4 2.0 Changes Document written from previous M95640/320/160/080 datasheet Announcement made of planned upgrade to 10MHz clock for the 5V, -40 to 85C, range TSSOP8 (3x3mm body size, MSOP8) package added New products, identified by the process letter W, added Correction to footnote in Ordering Information table Table of contents, and Pb-free options added. VIL(min) improved to - 0.45V MLP8 package added. Absolute Maximum Ratings for VIO(min) and VCC(min) improved. Soldering temperature information clarified for RoHS compliant devices. Device Grade 3 clarified, with reference to HRCF and automotive environments. Process identification letter "G" information added. SO8 narrow and TSSOP8 Package mechanical specifications updated. Product List summary table added. AEC-Q100-002 compliance. tHHQX corrected to tHHQV. 10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint clarified Added 20MHz and -S product information. Removed DIP package. Info on Pull-up resistors, VCC lines and Note 2. added to Figure 4.: Bus master and memory devices on the SPI bus. Device internal reset paragraph clarified. Packages compliant with the JEDEC Std J-STD-020C. Process info updated in DC and AC parameters and Table 32.: Ordering information scheme.
08-Jun-2004
3.0
07-Oct-2004
4.0
21-Sep-2005
5.0
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Revision history Table 35.
Date
M95160-x, M95080-x Document revision history (continued)
Revision Changes Document reformatted. Small text changes. TSSOP8 3 x 3 mm (DS) package removed, 1.65 V to 5.5 V operating voltage range removed (M95080-S and M95160-S removed). Figure 4: Bus master and memory devices on the SPI bus updated, note 2 removed and explanatory paragraph added (see Section 3: Connecting to the SPI bus). Section 2.7: VCC supply voltage and Section 2.8: VSS ground added. Power-up, Device Internal Reset and Power-down replaced by Section 4.1: Supply voltage (VCC). Command termination specified in Section 6.4: Write Status Register (WRSR). Blank process no longer available for M95160, M95080, M95160-W and M95080-W in the device grade 3 range. L, GB and SB processes no longer available for M95160 and M95080, in the device grade 6 range. L process no longer available for M95160-W and M95080-W in the device grade 6 range. ICC1 value and test conditions modified in Table 19: DC characteristics (M95160-R and M95080-R). End timing line of tSHQZ modified in Figure 17: Serial output timing. SO8N and UFDFPN8 package specifications updated. All packages are ECOPACK(R) compliant. Blank option removed below Plating technology and Note 2 modified in Table 32: Ordering information scheme. Table 33: Available M95160 products (package, voltage range, temperature grade) and Table 34: Available M95080 products (package, voltage range, temperature grade) added. Endurance modified on page 1. Small text changes. Section 4.1: Supply voltage (VCC) on page 12 modified. Section 6.6: Write to Memory Array (WRITE) on page 23 modified. Table 19: DC characteristics (M95160-R and M95080-R) updated. Note removed below Table 24: AC characteristics (M95160-W and M95080-W, device grade 6) on page 35. Inch values are calculated from millimeters and rounded to 4 decimal digits and UFDFPN package specifications updated (see Section 10: Package mechanical data on page 41). WLCSP (CS) package added (see Figure 20 and Table 30: WLCSP-R 1.350 x 1.365 mm 0.4 mm pitch 8 bumps, package mechanical data). M95160-F part number added (delivered in WLCSP package and device grade 6 only). Section 2.7: VCC supply voltage and Section 6.4: Write Status Register (WRSR) updated. Table 27: AC characteristics (M95160-F) added. Figure 15: Serial input timing, Figure 16: Hold timing and Figure 17: Serial output timing updated.
24-May-2007
6
06-Mar-2008
7
26-Jan-2009
8
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M95160-x, M95080-x Table 35.
Date
Revision history Document revision history (continued)
Revision Changes Section 4.1.2: Device reset updated. VRES added to DC characteristics tables 15, 16, 17, 18, 19 and 20. Note added to Section 6.6: Write to Memory Array (WRITE). Note 1 added to Table 19: DC characteristics (M95160-R and M95080-R). VIL and VOL modified in Table 20: DC characteristics (M95160-F). Table 24: AC characteristics (M95160-W and M95080-W, device grade 6) split into two tables: Table 24 for process GB or SB and Table 25 for process SA. M95160-F is now available in device grade 6 (Table 33: Available M95160 products (package, voltage range, temperature grade) updated. Revision number of 12-May-2009 corrected in Table 35: Document revision history. VRES corrected in Table 15: DC characteristics (M95160 and M95080, device grade 3) and Table 16: DC characteristics (M95160 and M95080, device grade 6).
12-May-2009
9
09-Oct-2009
10
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Price & Availability of M95160-FMN3GG

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